Bheemappa Halavar

According to our database, Bheemappa Halavar authored at least 7 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Performance Analysis of Weighted Victim Cache Replacement Policy.

Kartik Patel, Virendra Yadav, Uday Karra, Bheemappa Halavar

Proceedings of the 31st IEEE International Conference on High Performance Computing, Data and Analytics, HiPC 2024, 2024

2020

Power and performance analysis of 3D network-on-chip architectures.

Bheemappa Halavar, Basavaraj Talawar

Comput. Electr. Eng., 2020

2019

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures.

Bheemappa Halavar, Ujjwal Pasupulety, Basavaraj Talawar

Simul. Model. Pract. Theory, 2019

2018

Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip.

Bheemappa Halavar, Basavaraj Talawar

Proceedings of the 2018 International Conference on Signal Processing and Communications (SPCOM), 2018

Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures.

Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture.

Bheemappa Halavar, Basavaraj Talawar

Proceedings of the Intelligent Systems Design and Applications, 2018

Accurate Power and Latency Analysis of a Through-Silicon Via(TSV).

Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar

Proceedings of the 2018 International Conference on Advances in Computing, 2018