Chia-Yu Hsu
Orcid: 0000-0001-5488-8402Affiliations:
- Yuan Ze University, Department of Information Mangement, Chungli, Taiwan
- National Tsing Hua University, Department of Industrial Engineering and Engineering Management, Hsinchu, Taiwan
According to our database1,
Chia-Yu Hsu
authored at least 14 papers
between 2006 and 2024.
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Bibliography
2024
Guest editorial: Value chain collaboration for complicated product innovation and manufacturing excellence by industrial data-driven modeling and optimization.
Ind. Manag. Data Syst., 2024
Int. J. Prod. Res., 2024
2021
2018
Int. J. Comput. Intell. Syst., 2018
Foreword: Smart manufacturing, innovative product and service design to empower Industry 4.0.
Comput. Ind. Eng., 2018
2016
2015
A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing.
Comput. Oper. Res., 2015
2014
Overlay Error Compensation Using Advanced Process Control With Dynamically Adjusted Proportional-Integral R2R Controller.
IEEE Trans Autom. Sci. Eng., 2014
Manufacturing intelligence and innovation for digital manufacturing and operational excellence.
J. Intell. Manuf., 2014
2013
Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole.
Comput. Ind. Eng., 2013
2012
J. Intell. Manuf., 2012
2011
UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing.
J. Intell. Manuf., 2011
Manufacturing intelligence for determining machine subgroups to enhance yield in semiconductor manufacturning.
Proceedings of the Winter Simulation Conference 2011, 2011
2006
A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing.
J. Intell. Manuf., 2006