Dianyong Chen

According to our database, Dianyong Chen authored at least 8 papers between 2007 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel.

Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski

Proceedings of the UKSim'11, 2009

A Simulator for High-Speed Backplane Transceivers.

Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski

Proceedings of the UKSim'11, 2009

A monolithic high modulation efficiency CMOS laser diode / modulator driver.

Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang

Proceedings of the 2009 International Conference on Telecommunications, 2009

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel.

Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

A full-rate truly monolithic CMOS CDR for low-cost applications.

Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously.

Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2008

A 42-Gb/s Decision Circuit in 0.13µm CMOS.

Bangli Liang, Tad A. Kwasniewski, Dianyong Chen

Proceedings of the Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 2008

2007

Design Considerations for a Direct RF Sampling Mixer.

Dianyong Chen, Wei Wang, Tadeusz Kwasniewski

IEEE Trans. Circuits Syst. II Express Briefs, 2007