Erulappan Sakthivel

According to our database, Erulappan Sakthivel authored at least 6 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of seven.
• Erdős number of seven.

2018

BUTHA: Boost Up Clock Terminal with Heuristic Approach for NoC.

Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja

J. Circuits Syst. Comput., 2018

2017

Performance Improvement of Hardware/Software Architecture for Real-Time Bio Application Using MPSoC.

Raveendran Arun Prasath, Parasuraman Ganesh Kumar, Erulappan Sakthivel

Intell. Autom. Soft Comput., 2017

2016

An Adaptive Prediction Framework for Energy Efficient Wireless Sensor Networks.

Muruganantham Arunraja, Veluchamy Malathi, Erulappan Sakthivel

Ad Hoc Sens. Wirel. Networks, 2016

2015

Energy conservation in WSN through multilevel data reduction scheme.

Muruganantham Arunraja, Veluchamy Malathi, Erulappan Sakthivel

Microprocess. Microsystems, 2015

A New Simulator Based on Multi Core Processor with Improved Sense Amplifier.

Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja

J. Circuits Syst. Comput., 2015

2014

MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture.

Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja

Microprocess. Microsystems, 2014