Hyunwoo Jeong

Orcid: 0009-0001-9879-7067

According to our database¹, Hyunwoo Jeong authored at least 3 papers between 2024 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2025

A 2 A Dual Loop LDO With Dynamic Negative Feedback Loop and G<sub>m</sub> Boosting Error Amplifier for Off-Chip and Cap-Less Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025

A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

2024

8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Hyunwoo Jeong

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