Rastislav J. R. Struharik

Orcid: 0000-0002-7310-8173

According to our database1, Rastislav J. R. Struharik authored at least 16 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
CoNNa-Hardware accelerator for compressed convolutional neural networks.
Microprocess. Microsystems, 2020

2018
A system for hardware aided decision tree ensemble evolution.
J. Parallel Distributed Comput., 2018

CoNNA - Compressed CNN Hardware Accelerator.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
AIScale - A coarse grained reconfigurable CNN hardware accelerator.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Implementation of application specific instruction-set processor for the artificial neural network acceleration using LISA ADL.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Co-Processor for evolutionary full decision tree induction.
Microprocess. Microsystems, 2016

Coarse-grained reconfigurable hardware accelerator of machine learning classifiers.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2016

2015
Hardware acceleration of homogeneous and heterogeneous ensemble classifiers.
Microprocess. Microsystems, 2015

Reconfigurable Hardware for Machine Learning Applications.
J. Circuits Syst. Comput., 2015

Decision tree ensemble hardware accelerators for embedded applications.
Proceedings of the 13th IEEE International Symposium on Intelligent Systems and Informatics, 2015

2014
Inducing oblique decision trees.
Proceedings of the IEEE 12th International Symposium on Intelligent Systems and Informatics, 2014

2013
Hardware Implementation of Decision Tree Ensembles.
J. Circuits Syst. Comput., 2013

2012
IP cores for hardware evolution of decision trees.
Proceedings of the 10th IEEE Jubilee International Symposium on Intelligent Systems and Informatics, 2012

Design and verification of dynamically reconfigurable architecture.
Proceedings of the 10th IEEE Jubilee International Symposium on Intelligent Systems and Informatics, 2012

2009
Evolving Decision Trees in Hardware.
J. Circuits Syst. Comput., 2009

Intellectual property core implementation of decision trees.
IET Comput. Digit. Tech., 2009


  Loading...