Jia-Hui Bi

According to our database, Jia-Hui Bi authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

High-Speed Ultra-Energy-Efficient Memristor-Based Massive MIMO SIC Detector Circuit With Hybrid Analog-Digital Computing Architecture.

Jia-Hui Bi, Shaoshi Yang, Sheng Chen, Ping Zhang

IEEE Trans. Veh. Technol., July, 2025

2024

Accelerating Maximum-Likelihood Detection in Massive MIMO: A New Paradigm With Memristor Crossbar Based In-Memory Computing Circuit.

Yi-Hang Ren, Shaoshi Yang, Jia-Hui Bi, Yu-Xin Zhang

IEEE Trans. Veh. Technol., December, 2024

Amplifier-Enhanced Memristive Massive MIMO Linear Detector Circuit: An Ultra-Energy-Efficient and Robust-to-Conductance-Error Design.

Jia-Hui Bi, Shaoshi Yang, Ping Zhang, Sheng Chen

Proceedings of the 2024 IEEE Global Communications Conference, 2024

In-Memory Massive MIMO Linear Detector Circuit with Extremely High Energy Efficiency and Strong Memristive Conductance Deviation Robustness.

Jia-Hui Bi, Shaoshi Yang, Ping Zhang, Sheng Chen

Proceedings of the 2024 IEEE Global Communications Conference, 2024