Jianwei Jiang

According to our database1, Jianwei Jiang authored at least 9 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Wide-Range-Supply-Voltage Sense Amplifier Circuit for Embedded Flash Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Real-time hair simulation with heptadiagonal decomposition on mass spring system.
Graph. Model., 2020

2019
Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A charge pump system with new regulation and clocking scheme.
IEICE Electron. Express, 2019

Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design.
Proceedings of the International Conference on IC Design and Technology, 2019

2018
A novel highly reliable and low-power radiation hardened SRAM bit-cell design.
IEICE Electron. Express, 2018

A novel self-recoverable and triple nodes upset resilience DICE latch.
IEICE Electron. Express, 2018

A novel SEU tolerant memory cell for space applications.
IEICE Electron. Express, 2018

2009
Software System Design of 1GSps Embedded Digital Phosphor Oscilloscope.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009


  Loading...