Jianwen Cao
Orcid: 0000-0001-6786-192XAffiliations:
- University of Electronic Science and Technology of China, State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China
According to our database1,
Jianwen Cao
authored at least 8 papers
between 2017 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
An Integrated Gate Driver Based on SiC MOSFETs Adaptive Multi-Level Control Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
On-Chip Active Turn-Off Driving Technique to Prevent Channel Current From Disappearing Prematurely in SiC MOSFET's Applications.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
A Sub-Nanosecond Level Shifter with Ultra-High dV/dt Immunity Suitable for Wide-Bandgap Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck Converters.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Fully Integrated Floating Gate Driver with Adaptive Gate Drive Technique for High-Voltage Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
A high-precision voltage regulator with dynamic load technique and overcurrent protection.
Proceedings of the 12th IEEE International Conference on ASIC, 2017