Jiwanjot Singh

According to our database, Jiwanjot Singh authored at least 11 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Isolation Based Reduced Switch Nine-Level High-Gain Multilevel Inverter.

Dinesh Kumar Tiwari, Abhishek Kumar Singh, Nalin Behari Dev Choudhury, Jiwanjot Singh

IEEE Trans. Ind. Electron., April, 2025

Image Visibility Patch-Aided Partial Discharge Recognition Framework for Identifying Defects in XLPE Cables.

Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Soumya Chatterjee

IEEE Trans. Instrum. Meas., 2025

2024

Isolation-based bidirectional generalized step-up multilevel converter with optimized device count.

Dinesh Kumar Tiwari, Abhishek Kumar Singh, Nalin Behari Dev Choudhury, Jiwanjot Singh

Int. J. Circuit Theory Appl., September, 2024

A multi-objective low-voltage ride-through control strategy for three-phase grid-interfaced solar power plant during symmetrical and asymmetrical faults^{^†}.

Abhishek Kumar Singh, Dinesh Kumar Tiwari, Nalin Behari Dev Choudhury, Jiwanjot Singh

Int. J. Circuit Theory Appl., September, 2024

A modified modular multilevel converter to reduce the second order ripples in the submodule capacitor voltage: Design and analysis.

Ramudu Ganji, Jiwanjot Singh

Int. J. Circuit Theory Appl., July, 2024

2023

High-gain nine-level switched-capacitor multilevel inverter featuring less number of devices and leakage current.

Tamiru Debela Awas, Jiwanjot Singh

Int. J. Circuit Theory Appl., August, 2023

Automated Space Charge Classification Inside ±500-kV HVDC Cable Insulation Using Fusion of Superpixel and Deep Features for Remote Condition Assessment.

Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Arup Kumar Das, Soumya Chatterjee, Xiangrong Chen

IEEE Trans. Instrum. Meas., 2023

Characterization and Identification of Electrical Tree Growth Stages Inside High-Voltage Cable Insulation.

Sayanjit Singha Roy, Ashish Paramane, Jiwanjot Singh, Soumya Chatterjee, Zelin Hong, Xiangrong Chen

IEEE Trans. Instrum. Meas., 2023

2022

Evaluation of a grid-connected reduced-component boost multilevel inverter (BMLI) topology.

Tamiru Debela, Jiwanjot Singh, Vijay K. Sood

Int. J. Circuit Theory Appl., 2022

2020

Improvement in Fault Clearance Time of the Cascaded H-Bridge Multilevel Inverter Using Novel Technique Based on Frequency Detection.

Hillol Phukan, Jiwanjot Singh

Proceedings of the Modeling, Simulation and Optimization, 2020

Seven Level Enhanced Modified T-type Multilevel Inverter (MLI) with Reduce Part Count.

Hillol Phukan, Tamiru Debela, Jiwanjot Singh

Proceedings of the Modeling, Simulation and Optimization, 2020