Mathieu Escouteloup

According to our database, Mathieu Escouteloup authored at least 6 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

PowerSecBench: reveal microarchitectural power leakages using generic RISC-V microbenchmarks.

Mathieu Escouteloup, Vincent Migliore

Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

A Hardware Design Methodology to Prevent Microarchitectural Transition Leakages.

Mathieu Escouteloup, Vincent Migliore

Proceedings of the Constructive Approaches for Security Analysis and Design of Embedded Systems, 2025

2021

Garantir l'isolation microarchitecturale des processeurs. (Ensuring microarchitectural isolation in processors).

Mathieu Escouteloup

PhD thesis, 2021

Electromagnetic fault injection against a complex CPU, toward new micro-architectural fault models.

Thomas Trouchkine, Sébanjila Kevin Bukasa, Mathieu Escouteloup, Ronan Lashermes, Guillaume Bouffard

J. Cryptogr. Eng., 2021

Under the Dome: Preventing Hardware Timing Information Leakage.

Mathieu Escouteloup, Ronan Lashermes, Jacques Fournier, Jean-Louis Lanet

Proceedings of the Smart Card Research and Advanced Applications, 2021

2019

Electromagnetic fault injection against a System-on-Chip, toward new micro-architectural fault models.

Thomas Trouchkine, Sébanjila Kevin Bukasa, Mathieu Escouteloup, Ronan Lashermes, Guillaume Bouffard

CoRR, 2019