N. Siva Sankara Reddy

Orcid: 0000-0002-2733-3134

According to our database¹, N. Siva Sankara Reddy authored at least 3 papers between 2008 and 2025.

Collaborative distances:

Dijkstra number² of six.
Erdős number³ of five.

Timeline

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Bibliography

2025

A Read Delay Compensated and Write Assist SRAM Cell with Power Gated and Power Delay Product Reduction Circuitry.

[BibT_eX]

[DOI]

Mucherla Usha Rani

N. Siva Sankara Reddy

B. Rajendra Naik

J. Circuits Syst. Comput., 2025

2023

Hybrid Taguchi-Salp Swarm Optimization Based Energy Efficient MIMO System with Data Reordering and Scheduling Using Battle Royale Optimization Approach for the 5G Technologies.

[BibT_eX]

[DOI]

V. Shankar

N. Siva Sankara Reddy

Wirel. Pers. Commun., October, 2023

2008

Cascadable adiabatic logic circuits for low-power applications.

[BibT_eX]

[DOI]

N. Siva Sankara Reddy

M. Satyam

K. Lal Kishore

IET Circuits Devices Syst., 2008

N. Siva Sankara Reddy

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