Naruaki Hokari

According to our database, Naruaki Hokari authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

Enhancing the Readout Speed of NP-H-CAM Using Clocked CMOS Inverters.

Hisaya Sawada, Hirotaka Furukawa, Naruaki Hokari, Daishi Nishiguchi, Yujiro Harada, Masaaki Fukuhara

Proceedings of the IEEE Region 10 Conference, 2024

A Minimum Value Determination Circuit Using a Neuron CMOS WTA with FGC Circuit.

Naruaki Hokari, Hisaya Sawada, Hirotaka Furukawa, Tatsuya Hasegawa, Daishi Nishiguchi, Masaaki Fukuhara

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2024

A Neuron CMOS Type Full Subtractor with Floating Gate Calibration Circuit.

Hirotaka Furukawa, Hisaya Sawada, Naruaki Hokari, Tatsuya Hasegawa, Daishi Nishiguchi, Masaaki Fukuhara

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2024

2023

A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit.

Shoma Ito, Hisaya Sawada, Hirotaka Furukawa, Naruaki Hokari, Daishi Nishiguchi, Masaaki Fukuhara

Proceedings of the IEEE Region 10 Conference, 2023