Pavithara P

According to our database, Pavithara P authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

Design and Analysis of 4 Bit Multipliers Using Pass Transistor Logic and Gate Diffusion Input Technique Using 18nm FinFET Technology.

Pavithara P, Ramesh M, Prabu M, Kavin Kumar K, Ponmurugan P, Udaya Suriyan V

Proceedings of the 7th International Conference on Devices, Circuits and Systems, 2024

FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications.

Pavithara P, Raghapriya N. R, P. M. Dinesh, S. Gowtham, D. Viji, K. Kavin Kumar, Gokul Chandrasekaran

Proceedings of the 15th International Conference on Computing Communication and Networking Technologies, 2024

Low Power, High Speed Current Starved Ring Oscillator based ADC using 18nm FinFET Technology.

Gokul Chandrasekaran, Pavithara P, P. M. Dinesh, V. Arun Kumar, J. S. Sharanyanivasini, K. Kavin Kumar

Proceedings of the 15th International Conference on Computing Communication and Networking Technologies, 2024

2023

A Novel approach for Image Processing based on colluding of Raspberry-Pi and FPGA adopting IoT.

Pavithra M, Nirmaladevi P, Pavithara P, Banumithra B, Kawin S, Manoj Kumar D., Leander Antony G

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023