Po-Hsun Chu
According to our database1,
Po-Hsun Chu
authored at least 6 papers
between 2018 and 2025.
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Bibliography
2025
A 600-pW, 34.6 ppm/°C, -50 °C to 130 °C CMOS Voltage Reference with Leakage-Based Temperature Compensation and Supply Rejection Enhancement Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
StyleDiT: A Unified Framework for Diverse Child and Partner Faces Synthesis with Style Latent Diffusion Transformer.
CoRR, 2024
A Pulsed Electrochemistry Readout IC with Slew-rate Booting Technique and Phase-domain ΔΣ ADC for Si-Nanowire Electrical Double-layer Capacitance Measurement.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
ReActXGB: A Hybrid Binary Convolutional Neural Network Architecture for Improved Performance and Computational Efficiency.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024
Proceedings of the 46th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2024
2018
BMC Bioinform., 2018