Ramakant Yadav

Orcid: 0000-0001-5455-9799

According to our database1, Ramakant Yadav authored at least 4 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of seven.
  • Erdős number3 of six.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2025
Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI Applications.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2021
Double-gate line-tunneling field-effect transistor devices for superior analog performance.
Int. J. Circuit Theory Appl., 2021

2020
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger.
Microelectron. J., 2020

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC.
Integr., 2020


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