Saroja V. Siddamal

According to our database, Saroja V. Siddamal authored at least 13 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2024

2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues.

Dharmaray Nedalgi, Saroja V. Siddamal, S. S. Kerur

Integr., 2024

2023

Supply Noise and Peak Current Reduction in High-Speed Output Drivers.

Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability.

Dharmaray Nedalgi, Saroja V. Siddamal

J. Circuits Syst. Comput., 2022

Differential receiver with 2 × VDD input signals using 1 × VDD devices.

Dharmaray Nedalgi, Saroja V. Siddamal

Integr., 2022

2021

High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator.

Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter.

Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata S. Kotabagi, Nalini C. Iyer

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology.

Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2018

Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle.

Akashaykumar H. Sunagar, Saroja V. Siddamal

Proceedings of the 2018 International Conference on Advances in Computing, 2018

2014

Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology.

Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2008

Design of High-Speed Floating Point Multiplier.

Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008