Song Bian

According to our database1, Song Bian authored at least 21 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
NASS: Optimizing Secure Inference via Neural Architecture Search.
CoRR, 2020

2019
Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption.
IEICE Transactions, 2019

Are Powerful Graph Neural Nets Necessary? A Dissection on Graph Classification.
CoRR, 2019

SimGNN: A Neural Network Approach to Fast Graph Similarity Computation.
Proceedings of the Twelfth ACM International Conference on Web Search and Data Mining, 2019

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks.
IEEE Trans. on Circuits and Systems, 2018

Graph Edit Distance Computation via Graph Neural Networks.
CoRR, 2018

A study on NBTI-induced delay degradation considering stress frequency dependence.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

DWE: decrypting learning with errors with errors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.
IEICE Transactions, 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.
IEICE Transactions, 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

SCAM: Secured content addressable memory based on homomorphic encryption.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability.
IEICE Transactions, 2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.
Proceedings of the 25th IEEE Asian Test Symposium, 2016


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