Sujit K. Biswas

Orcid: 0000-0001-6993-7908

According to our database1, Sujit K. Biswas authored at least 12 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
A Rotor-Tied DFIG Scheme With One Phase Open Circuit Fault-Tolerant Capability.
IEEE Trans. Ind. Electron., May, 2025

Fault-Tolerant Control of Active Power Filter With Balanced Three-Phase Line Currents.
IEEE Trans. Ind. Electron., March, 2025

2024
Series Connected Open-End Winding Generator for Higher Voltage DC Supply.
IEEE Trans. Ind. Electron., June, 2024

A Fault-Tolerant Control Scheme of Grid Connected VSI for Balanced Power Injection.
IEEE Trans. Ind. Informatics, February, 2024

Three-Phase Open-End Induction Motor Drive Interfaced to Higher Voltage DC Bus.
IEEE Trans. Ind. Electron., February, 2024

2023
Phase-Controlled Multibank Resistive Heating With Optimized Current Harmonics.
IEEE Trans. Ind. Electron., October, 2023

A CB-PWM Technique for Eliminating CMV in Multilevel Multiphase VSI.
IEEE Trans. Ind. Electron., September, 2023

A Local Measurement Based Comprehensive Protection Scheme for AC Microgrid.
CoRR, 2023

2018
A Wide-Range TCR With Low-Current THD by Optimized Combination of Coupled Reactors and Thyristor Switching and Control.
IEEE Trans. Ind. Electron., 2018

2017
A New Harmonic Reduced Three-Phase Thyristor-Controlled Reactor for Static VAr Compensators.
IEEE Trans. Ind. Electron., 2017

Efficiency and Cost Optimized Design of an Induction Motor Using Genetic Algorithm.
IEEE Trans. Ind. Electron., 2017

Harmonic Cancellation in a Three-Phase Thyristor Controlled Reactor Using Dual Banks.
IEEE Trans. Ind. Electron., 2017


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