Trishna Rajkumar

Orcid: 0000-0002-1024-7897

According to our database1, Trishna Rajkumar authored at least 7 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
Exploring the Potential of LSTM On Emulating Multiple-bit Fault Injection in SRAM-FPGA.
Proceedings of the Computer Safety, Reliability, and Security, 2025

On Predictive Modeling of Multi-Bit Upsets for Emulated Fault Injection.
Proceedings of the 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025

2024
Navigating the Challenges of Statistical Fault Injection in SRAM-FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-Concept.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022
AnoDe: A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA.
Proceedings of the 27th IEEE Pacific Rim International Symposium on Dependable Computing, 2022

A Markovian Approach for Detecting Failures in the Xilinx SEM core.
Proceedings of the International Conference on Field-Programmable Technology, 2022


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