Vinayak Hande

According to our database, Vinayak Hande authored at least 6 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-Mode Range With <86 fJ · ns EDP.

Nidhi Sharma, Sherin A. Thomas, Vinayak Hande, Devarshi Mrinal Das

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

2024

BAG2-assisted analog layout synthesis for TSMC 65 nm and GPDK 45 nm.

Matthew Bio, Wolfgang Scherr, Andrew Selasi Agbemenu, Santiago Martin Sondón, Vinayak Hande, Johannes Sturm

Elektrotech. Informationstechnik, March, 2024

2022

6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction.

Nidhi Sharma, Vinayak Hande, Rajesh Kumar Srivastava, Devarshi Mrinal Das

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2018

Ultra low-energy active charge restoration DAC for SAR Analog-to-Digital Converter.

Japesh Vohra, Vinayak Hande

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

3 dB Bandwidth Enhancement using Miller Attenuation Technique.

Shivam Agarwal, Harsh Kumar, Vinayak Hande

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Ultra Low Power, Trimless and Resistor-less Bandgap Voltage Reference.

Kamal Jeet Singh, Rajesh Mehra, Vinayak Hande

Proceedings of the 13th IEEE International Conference on Industrial and Information Systems, 2018