Vinayak Hande

According to our database1, Vinayak Hande authored at least 6 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-Mode Range With <86 fJ · ns EDP.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

2024
BAG2-assisted analog layout synthesis for TSMC 65 nm and GPDK 45 nm.
Elektrotech. Informationstechnik, March, 2024

2022
6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2018
Ultra low-energy active charge restoration DAC for SAR Analog-to-Digital Converter.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

3 dB Bandwidth Enhancement using Miller Attenuation Technique.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Ultra Low Power, Trimless and Resistor-less Bandgap Voltage Reference.
Proceedings of the 13th IEEE International Conference on Industrial and Information Systems, 2018


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