William N. Carr

According to our database1, William N. Carr authored at least 3 papers between 1962 and 2007.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

1962
Bias-Controlled Tunnel-Pair Logic Circuits.
IRE Trans. Electron. Comput., 1962


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