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Y. R. Liu

According to our database1, Y. R. Liu authored at least 2 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation.
[BibTeX]
[DOI]
C. H. Sung
,
M. J. Huang
,
Y. J. Li
,
Y. T. Yang
,
Y. R. Liu
,
P. H. Shih
,
J. C. Guo
,
Steve S. Chung
Proceedings of the IEEE International Reliability Physics Symposium, 2025

2024
An Ultra-Low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator.
[BibTeX]
[DOI]
T. C. Kao
,
M. J. Huang
,
Y. R. Liu
,
Y. K. Wang
,
J. C. Guo
,
Steve S. Chung
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024


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