Yu Xie

Orcid: 0000-0002-4832-3453

Affiliations:
  • Beijing Institute of Technology, Beijing, China


According to our database1, Yu Xie authored at least 12 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
An ARM-FPGA Hybrid Acceleration and Fault Tolerant Technique for Phase Factor Calculation in Spaceborne Synthetic Aperture Radar Imaging.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2024

2023
Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology.
Remote. Sens., October, 2023

Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism.
Frontiers Comput. Neurosci., September, 2023

An FPGA-GPU Heterogeneous System and Implementation for On-Board Remote Sensing Data Processing.
Proceedings of the International Conference on Field Programmable Technology, 2023

Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2020
On-Board Wind Scatterometry.
Remote. Sens., 2020

2019
Implementation of a radix-2<sup>k</sup> fixed-point pipeline FFT processor with optimized word length scheme.
IEICE Electron. Express, 2019

2018
Variable-length and high-precision FFT processors based on configurable constant factor multipliers and memory reallocations.
IEICE Electron. Express, 2018

Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS.
IEICE Electron. Express, 2018

An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
A novel low-overhead fault tolerant parallel-pipelined FFT design.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017


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