Aashish Kumar Tiwary

According to our database, Aashish Kumar Tiwary authored at least 2 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

DP-VSA: DSP Packing-Based Vector Systolic Accelerator with Dual Precision Support on FPGAs.

Aashish Kumar Tiwary, Yathin Kumar Attuluri, Nanditha Rao

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

LUTAccel: Look-up-Table Based Vector Systolic Accelerator on FPGAs.

Aashish Kumar Tiwary, Saketh Gajawada, Jay Shah, Nanditha Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025