Agenor Polo

According to our database1, Agenor Polo authored at least 2 papers in 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2012
An address generator approach to the hardware implementation of a scalable Pease FFT core.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

FPGA-based discrete ambiguity function for stochastic linear time-variant channels.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012


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