Aiwu Ruan

According to our database, Aiwu Ruan authored at least 8 papers between 2011 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Reinforcement Learning-Based Markov-Decision Process (MDP) Implementation for SRAM FPGAs.

Aiwu Ruan, Aokai Shi, Liang Qin, Shiyang Xu, Yifan Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2016

A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs.

Aiwu Ruan, Haiyang Huang, Jingwu Wang, Yifan Zhao

J. Electron. Test., 2016

2014

A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs.

Aiwu Ruan, Bairui Jie, Li Wan, Junhao Yang, Chuanyin Xiang, Zujian Zhu, Yu Wang

Microelectron. Reliab., 2014

A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA.

Aiwu Ruan, Wei Tian, Bo Ni, Ke Wu

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A bitstream readback based FPGA test and diagnosis system.

T. Du, Aiwu Ruan, P. Li, Bairui Jie

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs.

Aiwu Ruan, Junhao Yang, Li Wan, Bairui Jie, Zhiqiang Tian

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis.

Aiwu Ruan, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, Peng Li

Microelectron. Reliab., 2013

2011

A new event driven testbench synthesis engine for FPGA emulation.

Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Ping Li

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011