Alexander Krupp

Affiliations:
  • Paderborn University, C-LAB, Paderborn, Germany


According to our database1, Alexander Krupp authored at least 13 papers between 2003 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2010
Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

A systematic approach to the test of combined HW/SW systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A verification plan for systematic verification of mechatronic systems.
PhD thesis, 2009

Systematic Model-in-the-Loop Test of Embedded Control Systems.
Proceedings of the Analysis, 2009

2007
Approach for a Formal Verification of a Bit-serial Pipelined Architecture.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

2006
An Extension of the Classification-Tree Method for Embedded Systems for the Description of Events.
Proceedings of the Second Workshop on Model Based Testing, 2006

Classification trees for random tests and functional coverage.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

TestML - A Test Exchange Language for Model-Based Testing of Embedded Software.
Proceedings of the Model-Driven Development of Reliable Automotive Services, 2006

2005
Die Klassifikationsbaummethode für eingebettete Systeme mit Testmustern für nichtkontinuierliche Reglerelemente.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

2004
Formal Refinement and Model Checking of an Echo Cancellation Unit.
Proceedings of the 2004 Design, 2004

2003
Formale Verfeinerung und Modelchecking von zeitbehafteten endlichen Automaten.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Combining Formal Refinement and Model Checking for Real-Time Systems Verification.
Proceedings of the Forum on specification and Design Languages, 2003


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