Allen C. Cheng
According to our database1,
Allen C. Cheng
authored at least 18 papers
between 2004 and 2012.
Collaborative distances:
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Bibliography
2012
Machine learning on-a-chip: A high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications.
Comput. Biol. Medicine, 2012
2011
SubsetTrio: An evolutionary, geometric, and statistical benchmark subsetting framework.
ACM Trans. Model. Comput. Simul., 2011
A self-healing autonomous neural network hardware for trustworthy biomedical systems.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
2010
A wearable smartphone-based platform for real-time cardiovascular disease detection via electrocardiogram processing.
IEEE Trans. Inf. Technol. Biomed., 2010
IEEE Trans. Biomed. Circuits Syst., 2010
2009
A programmable implementation of neural signal processing on a smartdust for brain-computer interfaces.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
ImplantBench: Characterizing and Projecting Representative Benchmarks for Emerging Bioimplantable Computing.
IEEE Micro, 2008
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study.
Proceedings of the 45th Design Automation Conference, 2008
2007
Accelerating Embedded Multimedia Applications with Versatile and Reconfigurable Instruction Fusion.
Proceedings of the Ninth IEEE International Symposium on Multimedia, 2007
2006
Application-specific architecture framework for high-performance low -power embedded computing.
PhD thesis, 2006
IBM J. Res. Dev., 2006
2005
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.
IEEE Trans. Computers, 2005
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
2004
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.
Proceedings of the 41th Design Automation Conference, 2004