Alok Naugarhiya

According to our database, Alok Naugarhiya authored at least 7 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Multi-Split SOI Super-Junction VDMOS: A TCAD Simulation Study of the Single-Event Effect.

Sanjeev Manoj Ranjan, Saikat Majumder, Alok Naugarhiya, Ashutosh Mishra, Amjad Gawanmeh

IEEE Access, 2026

2024

Endurance Behavior of Z-Shaped Charge Plasma Tunnel FET for Biosensing Application.

Ragini Singh, Alok Naugarhiya, Guru Prasad Mishra

J. Circuits Syst. Comput., January, 2024

Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application.

Shriharsh Prasad Behera, Mahesh Vaidya, Alok Naugarhiya

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology.

Abhishek Ray, Alok Naugarhiya, Guru Prasad Mishra

Microelectron. J., 2023

2022

Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application.

Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric.

Kumari Nibha Priyadarshani, Sangeeta Singh, Alok Naugarhiya

Microelectron. J., 2021

2020

An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times.

Ankush Chunn, Akshay Agrawal, Alok Naugarhiya

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020