Alpana Agarwal

According to our database, Alpana Agarwal authored at least 21 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A Scalable Fully-Digital Differential Analog Voltage Comparator.

Ashima Gupta, Anil Singh, Alpana Agarwal

J. Circuits Syst. Comput., 2022

Functional validation of highly synthesizable voltage comparator on FPGA.

Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal

Integr., 2022

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator.

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal

Int. J. Circuit Theory Appl., 2022

A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal

Circuits Syst. Signal Process., 2022

A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range.

Naveen Kandpal, Anil Singh, Alpana Agarwal

Circuits Syst. Signal Process., 2022

Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci series.

Amandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal

Biomed. Signal Process. Control., 2022

2021

Bidirectional transfer learning model for sentiment analysis of natural language.

Shivani Malhotra, Vinay Kumar, Alpana Agarwal

J. Ambient Intell. Humaniz. Comput., 2021

Entropy optimized semi-supervised decomposed vector-quantized variational autoencoder model based on transfer learning for multiclass text classification and generation.

Shivani Malhotra, Vinay Kumar, Alpana Agarwal

CoRR, 2021

2020

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology.

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal

J. Circuits Syst. Comput., 2020

A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal

J. Circuits Syst. Comput., 2020

Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC.

Ashima Gupta, Anil Singh, Alpana Agarwal

J. Circuits Syst. Comput., 2020

An Efficient R-Peak Detection Using Riesz Fractional-Order Digital Differentiator.

Amandeep Kaur, Sanjay Kumar, Alpana Agarwal, Ravinder Agarwal

Circuits Syst. Signal Process., 2020

2019

Fast digital foreground gain error calibration for pipelined ADC.

Jupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal

IET Circuits Devices Syst., 2019

Highly-digital voltage scalable 4-bit flash ADC.

Ashima Gupta, Anil Singh, Alpana Agarwal

IET Circuits Devices Syst., 2019

A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal

Proceedings of the Intelligent Systems and Applications, 2019

2017

A Digital-Based Low-Power Fully Differential Comparator.

Anil Singh, Ayushi Goel, Alpana Agarwal

J. Circuits Syst. Comput., 2017

Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology.

Anil Singh, Veena Rawat, Alpana Agarwal

IET Circuits Devices Syst., 2017

2013

A Combined CMOS Reference Circuit with Supply and Temperature Compensation.

Madhusoodan Agrawal, Alpana Agarwal

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2011

Synthesis of Analog IC Building Blocks.

Alpana Agarwal, Chandra Shekhar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2008

Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers.

Alpana Agarwal, Chandra Shekhar

VLSI Design, 2008

2004

Carry Circuitry for LUT-Based FPGA.

Varun Jindal, Alpana Agarwal

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004