Amir Attarha

According to our database1, Amir Attarha authored at least 9 papers between 2000 and 2002.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2002
Detecting signal-overshoots for reliability analysis in high-speed system-on-chips.
IEEE Trans. Reliab., 2002

Application of fuzzy logic in resistive fault modeling and simulation.
IEEE Trans. Fuzzy Syst., 2002

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs.
J. Electron. Test., 2002

Test Pattern Generation for Signal Integrity Faults on Long Interconnects.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Signal integrity fault analysis using reduced-order modeling.
Proceedings of the 39th Design Automation Conference, 2002

2001
Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing interconnects for noise and skew in gigahertz SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Built-In Self-Test for Signal Integrity.
Proceedings of the 38th Design Automation Conference, 2001

2000
Modeling and simulation of real defects using fuzzy logic.
Proceedings of the 37th Conference on Design Automation, 2000


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