Aranggan Venkataratnam

According to our database, Aranggan Venkataratnam authored at least 4 papers between 2001 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2008

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature.

Aranggan Venkataratnam, Ashok K. Goel

Microelectron. J., 2008

2006

Design and simulation of logic gates using single electron transistors at room temperature.

Aranggan Venkataratnam, Ashok K. Goel

Int. J. Comput. Sci. Eng., 2006

Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices.

Aranggan Venkataratnam, Ashok K. Goel

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

2001

Rapid prototyping of time-based PDIT for substrate networks [MCM] .

Aranggan Venkataratnam, Kimberly E. Newman

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001