Arka Dutta
Orcid: 0000-0001-5332-0751Affiliations:
- Jadavpur University, Department of Electronics and Telecommunication Engineering, Kolkata, India
According to our database1,
Arka Dutta
authored at least 12 papers
between 2014 and 2019.
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Bibliography
2019
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.
IET Circuits Devices Syst., 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2016
Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.
Microelectron. Reliab., 2016
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET.
Microelectron. Reliab., 2016
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance.
IET Circuits Devices Syst., 2016
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor.
IET Circuits Devices Syst., 2016
2015
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET.
Microelectron. J., 2015
J. Low Power Electron., 2015
2014
Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs.
Microelectron. Reliab., 2014
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
IET Circuits Devices Syst., 2014