Chandan Kumar Sarkar
According to our database1,
Chandan Kumar Sarkar
authored at least 52 papers
between 2006 and 2022.
Collaborative distances:
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Bibliography
2022
Introduction to the special section on State-of-the-art Micro-Nano devices and systems.
Comput. Electr. Eng., 2022
2020
IET Circuits Devices Syst., 2020
2019
Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures.
Microelectron. J., 2019
IET Circuits Devices Syst., 2019
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.
IET Circuits Devices Syst., 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IET Circuits Devices Syst., 2018
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing.
IET Circuits Devices Syst., 2018
2017
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application.
J. Low Power Electron., 2017
Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs.
IET Circuits Devices Syst., 2017
2016
Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs.
Microelectron. Reliab., 2016
Microelectron. Reliab., 2016
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET.
Microelectron. Reliab., 2016
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET.
ACM J. Emerg. Technol. Comput. Syst., 2016
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance.
IET Circuits Devices Syst., 2016
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor.
IET Circuits Devices Syst., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Microelectron. Reliab., 2015
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET.
Microelectron. J., 2015
Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs.
J. Low Power Electron., 2015
J. Low Power Electron., 2015
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application.
J. Circuits Syst. Comput., 2015
2014
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique.
J. Signal Process. Syst., 2014
Microelectron. Reliab., 2014
Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs.
Microelectron. Reliab., 2014
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
IET Circuits Devices Syst., 2014
2013
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme.
CoRR, 2013
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit.
CoRR, 2013
Proceedings of the Seventh International Conference on Sensing Technology, 2013
2012
Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions.
Microelectron. Reliab., 2012
Microelectron. J., 2012
1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model.
IET Circuits Devices Syst., 2012
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme.
Proceedings of the International Symposium on Electronic System Design, 2012
2011
Effects of La<sub>2</sub>O<sub>3</sub> incorporation in HfO<sub>2</sub> gated nMOSFETs on low-frequency noise.
Microelectron. Reliab., 2011
Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device.
Microelectron. Reliab., 2011
Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications.
IET Circuits Devices Syst., 2011
Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
2010
Electron transport in two dimensional electron gas formed at the heterojunction of Al<sub>x</sub>Ga<sub>(1-</sub><sub>x</sub><sub>)</sub>N/GaN at microwave frequencies.
Microelectron. Reliab., 2010
2009
Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications.
Microelectron. Reliab., 2009
Microelectron. Reliab., 2009
Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications.
Microelectron. Reliab., 2009
2008
A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain.
Microelectron. Reliab., 2008
2007
Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs.
Microelectron. Reliab., 2007
J. Electronic Imaging, 2007
Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis.
Proceedings of the IFIP VLSI-SoC 2007, 2007
2006
Comparative studies on electronic transport due to the reduced dimensionality at the heterojunctions of GaAs/A1<sub>x</sub>Ga<sub>(1-x)</sub>As and Ga<sub>x</sub>In<sub>(1-x)</sub>As/InP systems at low temperatures.
Microelectron. J., 2006