Arvind

Orcid: 0000-0003-0603-9865

Affiliations:
  • MIT, Cambridge, USA


According to our database1, Arvind authored at least 144 papers between 1973 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Experimental quantum state transfer of an arbitrary single-qubit state on a cycle with four vertices using a coined quantum random walk.
Quantum Inf. Process., November, 2023

Inferring physical laws by artificial intelligence based causal models.
CoRR, 2023

2022
Experimental demonstration of the dynamics of quantum coherence evolving under a PT-symmetric Hamiltonian on an NMR quantum processor.
Quantum Inf. Process., 2022

Efficient experimental characterization of quantum processes via compressed sensing on an NMR quantum processor.
Quantum Inf. Process., 2022

Efficient and Scalable Graph Pattern Mining on GPUs.
Proceedings of the 16th USENIX Symposium on Operating Systems Design and Implementation, 2022

Hemiola: A DSL and Verification Tools to Guide Design and Proof of Hierarchical Cache-Coherence Protocols.
Proceedings of the Computer Aided Verification - 34th International Conference, 2022

2021
Design of LSM-tree-based Key-value SSDs with Bounded Tails.
ACM Trans. Storage, 2021

A Case for Application-Managed Flash.
IEEE Trans. Computers, 2021

True experimental reconstruction of quantum states and processes via convex optimization.
Quantum Inf. Process., 2021

FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Effective simulation and debugging for a high-level hardware language using software compilers.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Identifying traffic of same keys in cryptographic communications using fuzzy decision criteria and bit-plane measures.
Int. J. Syst. Assur. Eng. Manag., 2020

A comparative study of system size dependence of the effect of non-unitary channels on different classes of quantum states.
Quantum Inf. Process., 2020

PinK: High-speed In-storage Key-value Store with Bounded Tails.
Proceedings of the 2020 USENIX Annual Technical Conference, 2020

The essence of Bluespec: a core language for rule-based hardware design.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

AQUOMAN: An Analytic-Query Offloading Machine.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Proteus: Language and Runtime Support for Self-Adaptive Software Development.
IEEE Softw., 2019

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications.
IEEE J. Solid State Circuits, 2019

Bit-Plane Specific Randomness Testing for Statistical Analysis of Ciphers.
Proceedings of the Soft Computing for Problem Solving 2019, 2019

MI6: Secure Enclaves in a Speculative Out-of-Order Processor.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

LightStore: Software-defined Network-attached Key-value Drives.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Experimentally identifying the entanglement class of pure tripartite states.
Quantum Inf. Process., 2018

Efficient experimental design of high-fidelity three-qubit quantum gates via genetic programming.
Quantum Inf. Process., 2018

Bit-Plane Specific Selective Histogram Equalization for Image Enhancement and Representation.
Proceedings of the Recent Trends in Image Processing and Pattern Recognition, 2018

Composable Building Blocks to Open up Processor Design.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Constructing a Weak Memory Model.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

GraFBoost: Using Accelerated Flash Storage for External Graph Analytics.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Low-power appliances for big-data analytics using flash storage and hardware accelerators.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Kami: a platform for high-level parametric hardware specification and its modular verification.
Proc. ACM Program. Lang., 2017

BigSparse: High-performance external graph analytics.
CoRR, 2017

Weak Memory Models with Matching Axiomatic and Operational Definitions.
CoRR, 2017

An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution.
CoRR, 2017

Lightweight KV-based Distributed Store for Datacenters.
Proceedings of the 9th USENIX Workshop on Hot Topics in Storage and File Systems, 2017

Terabyte Sort on FPGA-Accelerated Flash Storage.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
BlueDBM: Distributed Flash Storage for Big Data Analytics.
ACM Trans. Comput. Syst., 2016

BlueCache: A Scalable Distributed Flash-based Key-value Store.
Proc. VLDB Endow., 2016

Validating Simplified Processor Models in Architectural Studies.
CoRR, 2016

Taming Weak Memory Models.
CoRR, 2016

In-storage embedded accelerator for sparse pattern processing.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016

Application-Managed Flash.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

minFlash: A minimalistic clustered flash array.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Big Data Analytics on Flash Storage with Accelerators.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Quantum private comparison over noisy channels.
Quantum Inf. Process., 2015

Constructive computer architecture.
Proceedings of the Workshop on Computer Architecture Education, 2015

Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

BlueDBM: an appliance for big data analytics.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A transport-layer network for distributed FPGA platforms.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Modular Deductive Verification of Multiprocessor Hardware Designs.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

BlueDBM: A multi-access, distributed flash store for Big Data analytics.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
A new synthesis procedure for atomic rules containing multi-cycle function blocks.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

High-throughput implementation of a million-point sparse Fourier Transform.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Scalable multi-access flash store for big data analytics.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Modular compilation of guarded atomic actions.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Bluespec and Haskell.
Proceedings of the 1st annual workshop on Functional programming concepts in domain-specific languages, 2013

Leveraging rule-based designs for automatic power domain partitioning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Generating infrastructure for FPGA-accelerated applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A general technique for deterministic model-cycle-level debugging.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Fast and cycle-accurate modeling of a multicore processor.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Leveraging latency-insensitivity to ease multiple FPGA design.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Automatic generation of hardware/software interfaces.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
Improving performance and lifetime of solid-state drives using hardware-accelerated compression.
IEEE Trans. Consumer Electron., 2011

Verification of microarchitectural refinements in rule-based systems.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

WiLIS: Architectural modeling of wireless systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Automatic generation of hardware/software interfaces.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
IEEE Micro, 2010

A Comparative Evaluation of High-Level Hardware Synthesis Using Reed-Solomon Decoder.
IEEE Embed. Syst. Lett., 2010

A design flow based on modular refinement.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Is hardware innovation over?
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Airblue: a system for cross-layer wireless protocol development.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

Bounded Dataflow Networks and Latency-Insensitive circuits.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

2008
Advances in ESL Design.
IEEE Des. Test Comput., 2008

H.264 Decoder: A Case Study in Multiple Design Points.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract).
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Getting Formal Verification into Design Flow.
Proceedings of the FM 2008: Formal Methods, 2008

2007
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Scheduling as Rule Composition.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

2006
A Mobile Phone Ecosystem: MIT and Nokia's Joint Research Venture.
IEEE Intell. Syst., 2006

Store Atomicity for Transactional Memory.
Proceedings of the Thread Verification Workshop, 2006

UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

802.11a transmitter: a case study in microarchitectural exploration.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Memory Model = Instruction Reordering + Store Atomicity.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Research accelerator for multiple processors.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2005
Automatic synthesis of cache-coherence protocol processors using Bluespec.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Building up to macroprogramming: an intermediate language for sensor networks.
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005

2004
Operation-centric hardware description and synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Rate Guarantees and Overload Protection in Input-Queued Switches.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

High-level synthesis: an essential ingredient for designing complex ASICs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Rethinking Computer Architecture Research.
Proceedings of the High Performance Computing, 2004

Modular scheduling of guarded atomic actions.
Proceedings of the 41th Design Automation Conference, 2004

2003
Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

2001
Proofs of Correctness of Cache-Coherence Protocols.
Proceedings of the FME 2001: Formal Methods for Increasing Software Productivity, 2001

Implicit parallel programming in pH.
Morgan Kaufmann, ISBN: 978-1-55860-644-9, 2001

2000
From Monsoon to StarT-Voyager: University-Industry Collaboration.
IEEE Micro, 2000

Improving the Java memory model using CRF.
Proceedings of the 2000 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2000

Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Synthesis of Operation-Centric Hardware Descriptions.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Using term rewriting systems to design and verify processors.
IEEE Micro, 1999

Commit-Reconcile & Fences (CRF): A New Memory Model for Architects and Compiler Writers.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Hardware Synthesis from Term Rewriting Systems.
Proceedings of the VLSI: Systems on a Chip, 1999

CACHET: an adaptive cache coherence protocol for distributed shared-memory systems.
Proceedings of the 13th international conference on Supercomputing, 1999

1998
A Comparison of Implicitly Parallel Multithreaded and Data-Parallel Implementations of an Ocean Model.
J. Parallel Distributed Comput., 1998

LambdaS: an implicitly parallel lambda-calculus with letrec, synchronization and side-effects.
Proceedings of the 3rd International Workshop on High-Level Concurrent Languages, 1998

StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Message passing support on StarT-Voyager.
Proceedings of the 5th International Conference On High Performance Computing, 1998

The StarT-Voyager Parallel System.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1996
A Multithreaded Substrate and Compilation Model for the Implicity Parallel Language pH.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

A Lambda Calculus with Letrecs and Barriers.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1996

Performance tuning scientific codes for dataflow execution.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Properties of a First-Order Functional Language with Sharing.
Theor. Comput. Sci., 1995

Semantics of Barriers in a Non-Strict, Implicitly-Parallel Language.
Proceedings of the seventh international conference on Functional programming languages and computer architecture, 1995

START-NG: Delivering Seamless Parallel Computing.
Proceedings of the Euro-Par '95 Parallel Processing, 1995

1994
Prospects of ubiquitous parallel computing.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1993
Performance Studies of Id on the Monsoon Dataflow System.
J. Parallel Distributed Comput., 1993

The Evolution of Dataflow Architectures: from Static Dataflow to P-RISC.
Int. J. High Speed Comput., 1993

1992
*T: A Multithreaded Massively Parallel Architecture.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991
A Syntactic Approach to Program Transformations.
Proceedings of the Symposium on Partial Evaluation and Semantics-Based Program Manipulation, 1991

Compilation of Id.
Proceedings of the Languages and Compilers for Parallel Computing, 1991

M-Structures: Extending a Parallel, Non-strict, Functional Language with State.
Proceedings of the Functional Programming Languages and Computer Architecture, 1991

1990
Executing a Program on the MIT Tagged-Token Dataflow Architecture.
IEEE Trans. Computers, 1990

1989
I-Structures: Data Structures for Parallel Computing.
ACM Trans. Program. Lang. Syst., 1989

P-TAC: A Parallel Intermediate Language.
Proceedings of the fourth international conference on Functional programming languages and computer architecture, 1989

1988
Future Scientific Programming on Parallel Machines.
J. Parallel Distributed Comput., 1988

Resource Requirements of Dataflow Programs.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1987
Two Fundamental Issues in Multiprocessing.
Proceedings of the Parallel Computing in Science and Engineering, 1987

1986
Clarification of "Feeding Inputs on Demand" in Efficient Demand-Driven Evaluation - Part 1.
ACM Trans. Program. Lang. Syst., 1986

Efficient Demand-Driven Evaluation - Part 2.
ACM Trans. Program. Lang. Syst., 1986

1985
Efficient Demand-Driven Evaluation - Part 1.
ACM Trans. Program. Lang. Syst., 1985

Demand-Driven Evaluation on Dataflow Machine.
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1985

1984
Resource managers in functional programming.
J. Parallel Distributed Comput., 1984

1983
A Critique of Multiprocessing von Neumann Style
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1982
The U-Interpreter.
Computer, 1982

Data Flow Systems - Guest Editors' Introduction.
Computer, 1982

1981
Data Flow Languages and Architecture.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

1980
Streams and Managers.
Proceedings of the Operating Systems Engineering: Proceedings of the 14th IBM Computer SCience Symposium, 1980

1977
Indeterminancy, Monitors, and Dataflow.
Proceedings of the Sixth Symposium on Operating System Principles, 1977

Some Relationships Between Asynchronous Interpreters of a Dataflow Language.
Proceedings of the Formal Description of Programming Concepts: Proceedings of the IFIP Working Conference on Formal Description of Programming Concepts, 1977

A Computer Capable of Exchanging Processors for Time.
Proceedings of the Information Processing, 1977

1973
On Reference String Generation Processes.
Proceedings of the Fourth Symposium on Operating System Principles, 1973


  Loading...