Aurélien Cavelan

According to our database1, Aurélien Cavelan authored at least 20 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Coping with silent and fail-stop errors at scale by combining replication and checkpointing.
J. Parallel Distrib. Comput., 2018

Towards a Mini-App for Smoothed Particle Hydrodynamics at Exascale.
CoRR, 2018

Combining Checkpointing and Replication for Reliable Execution of Linear Workflows.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
Scheduling algorithms and resilience patterns for fail-stop and silent errors. (Algorithmes d'ordonnancement et schémas de résilience pour les pannes et les erreurs silencieuses).
PhD thesis, 2017

Towards Optimal Multi-Level Checkpointing.
IEEE Trans. Computers, 2017

Resilient N-Body Tree Computations with Algorithm-Based Focused Recovery: Model and Performance Analysis.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2017

Resilience for Stencil Computations with Latent Errors.
Proceedings of the 46th International Conference on Parallel Processing, 2017

Optimal Checkpointing Period with Replicated Execution on Heterogeneous Platforms.
Proceedings of the ACM Workshop on Fault-Tolerance for HPC at Extreme Scale, 2017

Identifying the Right Replication Level to Detect and Correct Silent Errors at Scale.
Proceedings of the ACM Workshop on Fault-Tolerance for HPC at Extreme Scale, 2017

2016
Assessing General-Purpose Algorithms to Cope with Fail-Stop and Silent Errors.
TOPC, 2016

Coping with recall and precision of soft error detectors.
J. Parallel Distrib. Comput., 2016

Two-Level Checkpointing and Verifications for Linear Task Graphs.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Optimal Resilience Patterns to Cope with Fail-Stop and Silent Errors.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

A Different Re-execution Speed Can Help.
Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

When Amdahl Meets Young/Daly.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

2015
Scheduling Independent Tasks with Voltage Overscaling.
Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

Assessing the Impact of Partial Verifications against Silent Data Corruptions.
Proceedings of the 44th International Conference on Parallel Processing, 2015

Voltage Overscaling Algorithms for Energy-Efficient Workflow Computations With Timing Errors.
Proceedings of the 5th Workshop on Fault Tolerance for HPC at eXtreme Scale, 2015

Which Verification for Soft Error Detection?
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2014
Assessing General-Purpose Algorithms to Cope with Fail-Stop and Silent Errors.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2014


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