Ayush Dahiya
Orcid: 0000-0002-5196-231X
According to our database1,
Ayush Dahiya authored at least 6 papers
between 2023 and 2026.
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Bibliography
2026
A low-power half-select free 8T SRAM cell with process-induced variation resistance for voltage scaling at 32 nm technology node.
Integr., 2026
2025
A Variation Tolerant Write Assist Read Decoupled 9T SRAM Cell for Low Voltage Application.
ACM Trans. Design Autom. Electr. Syst., September, 2025
2024
Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency.
ACM Trans. Design Autom. Electr. Syst., 2024
2023
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM.
ACM Trans. Design Autom. Electr. Syst., November, 2023
Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance.
Circuits Syst. Signal Process., October, 2023
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023