B. Jeevan

Orcid: 0000-0002-2126-0907

According to our database1, B. Jeevan authored at least 2 papers between 2021 and 2023.

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Bibliography

2023
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units.
Microprocess. Microsystems, June, 2023

2021
Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers.
Microelectron. J., 2021


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