B. Jeevan

Orcid: 0000-0002-2126-0907

According to our database¹, B. Jeevan authored at least 2 papers between 2021 and 2023.

Collaborative distances:

Timeline

Book In proceedings Article PhD thesis Dataset Other

2023

Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units.

[DOI]

Microprocess. Microsystems, June, 2023

2021

Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers.

[DOI]

Microelectron. J., 2021