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B. V. V. Satyanarayana

Orcid: 0000-0003-2601-7014

According to our database1, B. V. V. Satyanarayana authored at least 2 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Design Analysis of Memristor-Based 7T SRAM Using Heterojunction Tunneling Transistors.
[BibTeX]
[DOI]
Prasanna Kumar Godi
,
Prudhvi Raj Budumuru
,
A. Krishna Chaitanya Varma
,
B. V. V. Satyanarayana
,
Thoram Saran Kumar
,
Inukonda Rama Satya Nageswara Rao
J. Circuits Syst. Comput., 2025

2020
Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap.
[BibTeX]
[DOI]
B. V. V. Satyanarayana
,
Matta Durga Prakash
Microprocess. Microsystems, 2020


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