Bahram Rashidi

According to our database, Bahram Rashidi authored at least 34 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Fault-tolerant and error-correcting 4-bit S-boxes for cryptography applications with multiple errors detection.

Bahram Rashidi

J. Supercomput., January, 2024

Efficient and low-cost approximate multipliers for image processing applications.

Bahram Rashidi

Integr., January, 2024

2023

Error-correcting cryptographic S-boxes with multiple error detection and correction.

Bahram Rashidi

Int. J. Circuit Theory Appl., November, 2023

Lightweight Cryptographic S-Boxes Based on Efficient Hardware Structures for Block Ciphers.

Bahram Rashidi

ISC Int. J. Inf. Secur., 2023

2022

Glitch-less hardware implementation of block ciphers based on an efficient glitch filter.

Bahram Rashidi

Integr., 2022

2021

Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function.

Bahram Rashidi

Microelectron. J., 2021

Compact and efficient structure of 8-bit S-box for lightweight cryptography.

Bahram Rashidi

Integr., 2021

Lightweight 8-bit S-box and combined S-box/S-box-1 for cryptographic applications.

Bahram Rashidi

Int. J. Circuit Theory Appl., 2021

Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things.

Bahram Rashidi

IET Comput. Digit. Tech., 2021

2020

Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication.

Bahram Rashidi

J. Hardw. Syst. Secur., 2020

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher.

Bahram Rashidi

Int. J. Circuit Theory Appl., 2020

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher.

Bahram Rashidi

IET Comput. Digit. Tech., 2020

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED.

Bahram Rashidi

IET Circuits Devices Syst., 2020

2019

High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers.

Bahram Rashidi

Microelectron. J., 2019

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems.

Bahram Rashidi, Mohammad Abedini

J. Circuits Syst. Comput., 2019

High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers.

Bahram Rashidi

Int. J. Circuit Theory Appl., 2019

Efficient hardware structure for extended Euclidean-based inversion over F 2 m.

Bahram Rashidi

IET Comput. Digit. Tech., 2019

Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers.

Bahram Rashidi

IET Circuits Devices Syst., 2019

2018

Efficient hardware implementations of point multiplication for binary Edwards curves.

Bahram Rashidi

Int. J. Circuit Theory Appl., 2018

2017

High-speed hardware implementation of Gaussian normal basis inversion algorithm over F_2^m.

Bahram Rashidi

Microelectron. J., 2017

High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2<i> ^m </i>).

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

IET Inf. Secur., 2017

Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications.

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

IET Circuits Devices Syst., 2017

Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2<i> ^m </i>) for elliptic curve cryptosystems.

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

IET Circuits Devices Syst., 2017

High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves.

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

IACR Cryptol. ePrint Arch., 2017

A Survey on Hardware Implementations of Elliptic Curve Cryptosystems.

Bahram Rashidi

CoRR, 2017

2016

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems.

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

Microelectron. J., 2016

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2^m).

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

Integr., 2016

Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2<i> ^m </i>).

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

IET Comput. Digit. Tech., 2016

High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m).

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

IACR Cryptol. ePrint Arch., 2016

2015

Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields.

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

ISC Int. J. Inf. Secur., 2015

Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems.

Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi

IACR Cryptol. ePrint Arch., 2015

2014

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm.

Reza Rezaeian Farashahi, Bahram Rashidi, Sayed Masoud Sayedi

Microelectron. J., 2014

High-speed and pipelined finite field bit-parallel multiplier over GF(2^m) for elliptic curve cryptosystems.

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

Proceedings of the 11th International ISC Conference on Information Security and Cryptology, 2014

2013

High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA.

Bahram Rashidi

IET Signal Process., 2013