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Belal Jahannia

Orcid: 0009-0009-7924-3366

According to our database1, Belal Jahannia authored at least 4 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
DaLAMED: A Clock-Frequency and Data-Lifetime-Aware Methodology for Energy-Efficient Memory Design in Edge Devices.
[BibTeX]
[DOI]
Belal Jahannia
,
Abdolah Amirany
,
Elham Heidari
,
Hamed Dalir
IEEE Access, 2025

2024
An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications.
[BibTeX]
[DOI]
Belal Jahannia
,
Seyed Ali Ghasemi
,
Hamed Farbeh
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes.
[BibTeX]
[DOI]
Belal Jahannia
,
Seyed Ali Ghasemi
,
Hamed Farbeh
IEEE Access, 2024

2022
GraphA: An efficient ReRAM-based architecture to accelerate large scale graph processing.
[BibTeX]
[DOI]
Seyed Ali Ghasemi
,
Belal Jahannia
,
Hamed Farbeh
J. Syst. Archit., 2022


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