Bhavin Odedara

According to our database, Bhavin Odedara authored at least 3 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSD.

Pikul Sarkar, Nitin Gupta, Pallat Aravind, Bhavin Odedara, Dror Shahar

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2018

A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling.

Ankit Rehani, Sujay Deb, Pydi Ganga Bahubalindruni, Bhavin Odedara, Srikanth Bojja

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process.

Bhavin Odedara, Srikanth Bojja, Nitin Gupta, Igor Rapoport, Tony Ross, Alik Zelichenok

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017