Sujay Deb

Orcid: 0000-0002-6247-8718

According to our database1, Sujay Deb authored at least 96 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023).
IEEE Des. Test, December, 2023

2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs.
ACM J. Emerg. Technol. Comput. Syst., July, 2023

ReDeSIGN: Reuse of Debug Structures for Improvement in Performance Gain of NoC Based MPSoCs.
IEEE Trans. Emerg. Top. Comput., 2023

NoxyGen: A Network-On-Chip RTL Generator and Validation Tool.
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023

A Cortex M0 SoC Based IoT Platform for Agricultural Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2022
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures.
ACM Trans. Design Autom. Electr. Syst., 2022

Securing an Accelerator-Rich System From Flooding-Based Denial-of-Service Attacks.
IEEE Trans. Emerg. Top. Comput., 2022

Interconnect support for energy efficient and high bandwidth memory access in CMPs.
Sustain. Comput. Informatics Syst., 2022

Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures.
IEEE Des. Test, 2022

Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet Architectures.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems.
ACM Trans. Design Autom. Electr. Syst., 2021

WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Sniffer: A Machine Learning Approach for DoS Attack Localization in NoC-Based SoCs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

A Study on Securing Data in Smart Healthcare Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Smart Camera for Enforcing Social Distancing.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Mostly Passive Δ - Σ ADC with a-IGZO TFTs for Flexible Electronics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Low-Noise Energy Efficient Readout Front-End for Wearable Continuous Blood Pressure Monitoring Systems.
IEEE Trans. Consumer Electron., 2020

Designing of an Optimization Technique for the Prediction of CTS Outcomes using Neural Network.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Security Threats in Channel Access Mechanism of Wireless NoC and Efficient Countermeasures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures.
ACM Trans. Design Autom. Electr. Syst., 2019

Millimeter wave wireless interconnects in deep submicron chips: Challenges and opportunities.
Integr., 2019

Sixth-order differential Sallen-and-Key switched capacitor LPF using a-IGZO TFTs.
Int. J. Circuit Theory Appl., 2019

Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Energy-and Performance-Aware Router Design for Chip Multiprocessors.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Efficient Hardware Verification Using Machine Learning Approach.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Bootstrapping Circuit with IGZO TFTs for On-Chip Power Supply Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Biopotential acquisition unit for energy-efficient wearable health monitoring.
IET Cyper-Phys. Syst.: Theory & Appl., 2018

A PVT Insensitive Low-Power Differential Ring Oscillator.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

On-Chip Wireless Channel Propagation: Impact of Antenna Directionality and Placement on Channel Performance.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Dynamic NoC platform for varied application needs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A Low-Cost Smart Vein Viewer System.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Near Threshold Last Level Cache for Energy Efficient Embedded Applications.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Reliability Analysis of On-Chip Wireless Links for Many Core WNoCs.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Data-flow Aware CNN Accelerator with Hybrid Wireless Interconnection.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Adaptive Multi-Voltage Scaling with Utilization Prediction for Energy-Efficient Wireless NoC.
IEEE Trans. Sustain. Comput., 2017

Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas.
IEEE Trans. Multi Scale Comput. Syst., 2017

HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures.
IEEE Trans. Computers, 2017

P<sup>2</sup>NoC: Power- and Performance-aware NoC Architectures for Sustainable Computing.
Sustain. Comput. Informatics Syst., 2017

Energy efficient EEG acquisition and reconstruction for a Wireless Body Area Network.
Integr., 2017

Energy-Efficient Transceiver for Wireless NoC.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Enhancing Retention Voltage for SRAM.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Pseudo-BIST: A Novel Technique for SAR-ADC Testing.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Path loss-aware adaptive transmission power control scheme for energy-efficient wireless NoC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

OFDM Based High Data Rate, Fading Resilient Transceiver for Wireless Networks-on-Chip.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Energy efficient biopotential acquisition unit for wearable health monitoring applications.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Smart mobility solution with multiple input Output interface.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
Energy Efficient and Congestion-Aware Router Design for Future NoCs.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An effective and efficient algorithm to analyse and debug clock propagation issues.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Energy-efficient reconfigurable framework for evaluating hybrid NoCs.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Face video based touchless blood pressure and heart rate estimation.
Proceedings of the 18th IEEE International Workshop on Multimedia Signal Processing, 2016

Power efficient router architecture for wireless Network-on-Chip.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

A sparse regression based approach for cuff-less blood pressure measurement.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

An affordable cuff-less blood pressure estimation solution.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Adaptive multi-voltage scaling in wireless NoC for high performance low power applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A multi-signal acquisition system for preventive cardiology with cuff-less BP measurement capability.
Proceedings of the 8th International Conference on Communication Systems and Networks, 2016

2015
A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture.
Proceedings of the 28th International Conference on VLSI Design, 2015

Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring.
Proceedings of the 28th International Conference on VLSI Design, 2015

Analysis and design guidelines for customized logic families in CMOS.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A novel approach to reusable time-economized STIL based pattern development.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Achievable Performance Enhancements with mm-Wave Wireless Interconnects in NoC.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Energy Efficient Analog-to-Information Converter for Biopotential Acquisition Systems.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Power- and performance-aware fine-grained reconfigurable router architecture for NoC.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

2014
UVM based STBUS verification IP for verifying SoC architectures.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

An energy efficient wireless Network-on-Chip using power-gated transceivers.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Wireless network-on-chip: a new era in multi-core chip design.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Cuffless BP measurement using a correlation study of pulse transient time and heart rate.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Energy efficient acquisition and reconstruction of EEG signals.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013
Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects.
IEEE Trans. Computers, 2013

Energy efficient on-chip wireless interconnects with sleepy transceivers.
Proceedings of the 8th International Design and Test Symposium, 2013

Design space exploration for reliable mm-wave wireless NoC architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Energy-Efficient Network-on-Chip Architectures for Multi-Core Systems.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Performance evaluation and design trade-offs for wireless network-on-chip architectures.
ACM J. Emerg. Technol. Comput. Syst., 2012

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Design of an efficient NoC architecture using millimeter-wave wireless links.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Designing an intelligent blink analyzer tool for effective human computer interaction through eye.
Proceedings of the 4th International Conference on Intelligent Human Computer Interaction, 2012

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems.
IEEE Trans. Computers, 2011

2010
Comparative performance evaluation of wireless and optical NoC architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


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