Bill Moyer

According to our database1, Bill Moyer authored at least 9 papers between 1984 and 2002.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2002
Embedded cache architecture with programmable write buffer support for power and performance flexibility.
Proceedings of the International Conference on Compilers, 2002

2001
Low-power design for embedded processors.
Proc. IEEE, 2001

2000
A low power unified cache architecture providing power and performance flexibility (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

The M·CORE<sup>TM</sup> M340 Unified Cache Architecture.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A programmable unified cache architecture for embedded applications.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Instruction fetch energy reduction using loop caches for embedded applications with small tight loops.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Designing the M·CORE<sup>TM</sup> M3 CPU Architecture.
Proceedings of the IEEE International Conference On Computer Design, 1999

1984
The Motorola MC68020.
IEEE Micro, 1984


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