Byron Navas

According to our database, Byron Navas authored at least 7 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

AHA: Design and Evaluation of Compute-Intensive Hardware Accelerators for AMD-Xilinx Zynq SoCs Using HLS IP Flow.

David Berrazueta-Mena, Byron Navas

Comput., 2025

2015

Cognitive and Self-Adaptive SoCs with Self-Healing Run-Time-Reconfigurable RecoBlocks.

Byron Navas

PhD thesis, 2015

Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs.

Byron Navas, Ingo Sander, Johnny Öberg

Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

2014

On providing scalable self-healing adaptive fault-tolerance to RTR SoCs.

Byron Navas, Johnny Öberg, Ingo Sander

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

The upset-fault-observer: A concept for self-healing adaptive fault tolerance.

Byron Navas, Johnny Öberg, Ingo Sander

Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013

Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis.

Byron Navas, Johnny Öberg, Ingo Sander

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks.

Byron Navas, Ingo Sander, Johnny Öberg

Proceedings of the Design, Automation and Test in Europe, 2013