Cédric Marchand

Affiliations:
  • Univ. de Bretagne Sud, Lorient, France


According to our database1, Cédric Marchand authored at least 19 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
The Best, the Requested, and the Default Elementary Check Node for EMS NB-LDPC Decoder.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

Buffers optimization for multi-core decoders.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

Rate-Adaptive Cyclic Complex Spreading Sequence for Non-Binary Decoders.
Proceedings of the 12th International Symposium on Topics in Coding, 2023

2022
Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing.
J. Signal Process. Syst., 2022

2021
Parallel CN-VN processing for NB-LDPC decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

The Best, The Requested, and The Default Non-Binary LDPC Decoding Algorithm.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

Rate-adaptive Inner Code for Non-Binary Decoders.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

2019
Hybrid Check Node Architectures for NB-LDPC Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2017
Extended-forward architecture for simplified check node processing in NB-LDPC decoders.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

2016
Pre-Sorted Forward-Backward NB-LDPC Check Node Architecture.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

NB-LDPC check node with pre-sorted input.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

2015
LDPC decoder architecture for DVB-S2 and DVB-S2X standards.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

2014
Simplified Compression of Redundancy Free Trellis Sections in Turbo Decoder.
IEEE Commun. Lett., 2014

2013
High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

2012
Design and implementation of a near maximum likelihood decoder for Cortex codes.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

2011
Architecture and Finite Precision Optimization for Layered LDPC Decoders.
J. Signal Process. Syst., 2011

2010
Hardware Discrete Channel Emulator.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

2009
Conflict resolution for pipelined layered LDPC decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009


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