Pierre Bomel

According to our database1, Pierre Bomel authored at least 30 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Bi-Objective Cost Function for Adaptive Routing in Network-on-Chip.
IEEE Trans. Multi-Scale Computing Systems, 2018

Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip.
Microprocess. Microsystems, 2018

Bit-accurate energy estimation for Networks-on-Chip.
J. Syst. Archit., 2017

Energy Savings in Networks-on-Chip with Smart Temporal Shielding.
J. Low Power Electron., 2017

Energy aware Networks-on-Chip cortex inspired communication.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Heuristic Based Routing Algorithm for Network on Chip.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Crosstalk-aware link power model for Networks-on-Chip.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Virtual Devices for Hot-Pluggable Processors.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Orcc's compa-backend demonstration.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Virtual UARTs for Reconfigurable Multi-processor Architectures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Functional validation of AADL models via model transformation to SystemC with ATL.
Proceedings of the 5th International Workshop on Model Based Architecting and Construction of Embedded Systems, 2012

Hardware Discrete Channel Emulator.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Ultra-Fast Downloading of Partial Bitstreams through Ethernet.
Proceedings of the Architecture of Computing Systems, 2009

A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Embed. Syst., 2008

Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

A Networked, Lightweight and Partially Reconfigurable Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Constrained algorithmic IP design for system-on-chip.
Integr., 2007

A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embedded Comput. Syst., 2006

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI
CoRR, 2006

DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context.
Proceedings of the Embedded Computer Systems: Architectures, 2005

High-level synthesis under I/O timing and memory constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

C-based rapid prototyping for digital signal processing.
Proceedings of the 13th European Signal Processing Conference, 2005

High-Level Synthesis in Latency Insensitive System Methodology.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Hardware Virtual Components Compliant with Communication System Standards.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Synchronization Processor Synthesis for Latency Insensitive Systems.
Proceedings of the 2005 Design, 2005

Memory accesses management during high level synthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004