Chan Shan

Orcid: 0000-0003-4055-6583

According to our database¹, Chan Shan authored at least 3 papers between 2015 and 2026.

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Timeline

Book In proceedings Article PhD thesis Dataset Other

2026

Simulation and design of asymmetric vertical cladding layer-based tunneling field effect transistors with improved DC and Analog/RF performance.

[DOI]

Microelectron. J., 2026

2022

An n-MOSFET Layout with Multi-Finger Z Gate for Radiation Tolerance.

[DOI]

Proceedings of the 5th IEEE International Conference on Knowledge Innovation and Invention, 2022

2015

Improved performance of nanoscale junctionless transistor based on gate engineering approach.

[DOI]

Microelectron. Reliab., 2015