Changsok Han

According to our database1, Changsok Han authored at least 19 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators.
IEEE J. Solid State Circuits, 2022

2021
Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal Feedforward.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2019
Continuous-Time Delta-Sigma Modulator with Time Domain Noise Coupling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Study of Quantizer-Bandwidth in Continuous-Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Can SMASH Smash MASH?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A continuous-time delta-sigma modulator with self-ELD compensated quantizer.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer.
IEEE J. Solid State Circuits, 2017

A 200MS/s 7bit time domain ring quantizer.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Continuous-time delta-sigma modulator with maximally flat signal transfer function using minimum number of DACs.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizer.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator.
IEEE J. Solid State Circuits, 2016

SMASH-MASH delta-sigma modulator using noise-shaping quantizers.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A nano-ampere 2nd order temperature-compensated CMOS current reference using only single resistor for wide-temperature range applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multi-stage delta-sigma modulator with a relaxed opamp gain using a back-end digital integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Noise-cancelling sturdy MASH delta-sigma modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Time-Interleaved Noise-Coupling Delta-Sigma Modulator Using Modified Noise-Shaped Integrating Quantizer.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Continuous time delta-sigma modulator with an embedded passive low pass filter.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Sturdy-MASH delta-sigma modulator with noise-shaped integrating quantizer and dual-DAC DWA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Noise-Shaped Residue-Discharging Delta-Sigma ADCs With Time-Modulated Pulse Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014


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